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Freescale Semiconductor /MK02F12810 /SIM /SOPT8

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Interpret as SOPT8

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTM0SYNCBIT 0 (0)FTM1SYNCBIT 0 (0)FTM2SYNCBIT 0 (0)FTM0OCH0SRC 0 (0)FTM0OCH1SRC 0 (0)FTM0OCH2SRC 0 (0)FTM0OCH3SRC 0 (0)FTM0OCH4SRC 0 (0)FTM0OCH5SRC

FTM0OCH2SRC=0, FTM0OCH5SRC=0, FTM1SYNCBIT=0, FTM0OCH3SRC=0, FTM2SYNCBIT=0, FTM0OCH0SRC=0, FTM0OCH1SRC=0, FTM0OCH4SRC=0, FTM0SYNCBIT=0

Description

System Options Register 8

Fields

FTM0SYNCBIT

FTM0 Hardware Trigger 0 Software Synchronization

0 (0): No effect

1 (1): Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
FTM1SYNCBIT

FTM1 Hardware Trigger 0 Software Synchronization

0 (0): No effect.

1 (1): Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
FTM2SYNCBIT

FTM2 Hardware Trigger 0 Software Synchronization

0 (0): No effect.

1 (1): Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
FTM0OCH0SRC

FTM0 channel 0 output source

0 (0): FTM0_CH0 pin is output of FTM0 channel 0 output

1 (1): FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
FTM0OCH1SRC

FTM0 channel 1 output source

0 (0): FTM0_CH1 pin is output of FTM0 channel 1 output

1 (1): FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
FTM0OCH2SRC

FTM0 channel 2 output source

0 (0): FTM0_CH2 pin is output of FTM0 channel 2 output

1 (1): FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
FTM0OCH3SRC

FTM0 channel 3 output source

0 (0): FTM0_CH3 pin is output of FTM0 channel 3 output

1 (1): FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
FTM0OCH4SRC

FTM0 channel 4 output source

0 (0): FTM0_CH4 pin is output of FTM0 channel 4 output

1 (1): FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
FTM0OCH5SRC

FTM0 channel 5 output source

0 (0): FTM0_CH5 pin is output of FTM0 channel 5 output

1 (1): FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data